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Mentor Graphics Unveils Project Atlanta for Next-Generation Programmable Logic Synthesis
WILSONVILLE, Ore.--(BUSINESS WIRE)--Aug. 6, 2001--Mentor Graphics
Corporation today unveiled a technology roadmap defining its new
approach for next-generation programmable logic synthesis.
Named ``Project Atlanta,'' the roadmap calls for new synthesis
technology to be delivered in three phases over the next 18-months:
Phase I - Heuristic Synthesis; Phase II - Physical Synthesis; Phase
III - High-Level Synthesis. The first phase of Project Atlanta will be
released into a beta program in the fourth quarter of 2001.
As part of this initiative, Mentor Graphics has mobilized a
research and development team of noted synthesis experts,
significantly increasing the company's overall focus on FPGA
synthesis. The team includes scientists and hardware and software
development engineers from all areas of synthesis, including Register
Transfer Level (RTL), physical and behavioral. These resources will be
pooled into the new FPGA Synthesis business unit.
``The advent of system-on-chip (SoC) designs on programmable logic
platforms requires EDA vendors to adapt their tool offerings to deal
with unprecedented technical challenges, including massive frequency
increases and exponential gate count growth,'' said Dr. Walden C.
Rhines, chairman of the board and chief executive officer for Mentor
Graphics. ``In the programmable logic market, technology and chip
complexity are moving faster than anticipated. In order to remain
ahead of the curve, Mentor Graphics has turned significant corporate
resources to this market space.''
Requirements for Next Generation Synthesis
Fabrication process improvements down to 0.13-micron enable
high-frequency, multi-million gate SoC devices to be built on a
programmable platform. To preserve the time-to-market benefits of
these programmable devices as they increase in complexity, design
tools must be available in parallel with new device releases.
Synthesis tools must maximize usable gate count in devices with
embedded processors and extensive on-chip interconnect and
peripherals. To that end, Mentor Graphics has long-standing technology
partnerships with programmable device market leaders, Altera Corp.
(Nasdaq: ALTR) and Xilinx, Inc. (Nasdaq: XLNX - ), to deliver synthesis
for all new devices released by the vendors.
Roadmap Points to Key Issues in Programmable Logic Synthesis
In phase one, Mentor will focus on a new approach to FPGA
synthesis known as Heuristic Synthesis. Heuristic synthesis
incorporates years of design knowledge into the synthesis tool
enabling it to focus on larger building blocks in the design, such as
CPUs, ROMs, RAM, CAMs, etc., to build very fast and efficient
structures. In addition to the quality of results benefits, Heuristic
synthesis infers design intent reducing the time required to create
complex architectures, increasing simulation performance and
decreasing the design complexity.
In phase two, Mentor Graphics will deliver the industry's only
true physical optimization solution for FPGAs. Leveraging technology
from Mentor's leading ASIC timing closure tool, TeraPlace(TM), phase
two will merge physical information and data with synthesis
algorithms. FPGA designers will be able to improve design performance
by replacing inaccurate wire load models with data that properly
accounts for interconnect delays.
Phase three will make available synthesis software that enables
designers to design at a higher level of abstraction, allowing for
rapid design exploration and implementation.
Organized for Success
The new Mentor Graphics® synthesis business unit brings together
resources from the Exemplar Logic and the TeraPlace teams. Mentor is
uniquely positioned to address the programmable logic market, with
products in design capture, simulation, synthesis, co-verification,
formal verification, embedded systems, and intellectual property,
coupled with its STAR-award winning Customer Support team.
About Mentor Graphics Corporation
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of more
than $600 million and employs approximately 2,975 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics is a registered trademark of Mentor Graphics
Corporation. TeraPlace is a trademark of Mentor Graphics Corporation.
All other company or product names are the registered trademarks or
trademarks of their respective owners.
Contact:
Mentor Graphics Corp.
Keri Wilson
503/685.1359
keri_wilson@mentor.com
or
Benjamin Group/BSMG Worldwide
Jeremiah Glodoveza
415/352.2628 ext. 136
jglodoveza@bsmg.com
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